I'm Jungin, PhD candidate in Computer Architecture and Systems Lab at KAIST, co-advised by Jongse Park and Jeehoon Kang. My research interest lies in between hardware design and programming languages, aiming to bridge the gap between complex hardware and intuitive programming.

Other then my research, I like to run, work out at gym, play guitar, sing, and write blog posts.

Here, I'll be documenting the journey throughout my PhD, delving into my research, and sharing thoughts on life inside and outside academia.

Contact

• Email: jungin.rhee@kaist.ac.kr
• Github: jirheee
• Bibliography: ORCID
• Place: Rm. 4441, Bldg. E3-1, KAIST (+82-42-350-7878)

Publications

• (PLDI 2024) Modular Hardware Design of Pipelined Circuits with Hazards.
  • Minseong Jang, Jung In Rhee, Woojin Lee, Shuangshuang Zhao, Jeehoon Kang.
  • ACM SIGPLAN conference on Programming Languages Design and Implementation.
  • [paper: doi] ​ ​ ​

Education

• (2025-Current) Ph.D. in AI Semiconductor. KAIST.

• (2025) M.S. in Computer Science. KAIST.

• (2023) B.S. in Computer Science. KAIST.

Teaching

• Teaching Assistant, KAIST CS220 Programming Principles, Spring 2023
• Teaching Assistant, KAIST CS220 Programming Principles, Fall 2023
• Teaching Assistant, KAIST CS220 Programming Principles, Fall 2024
• Teaching Assistant, KAIST AS602 AI Semiconductor Paper Writing, Spring 2025

Honors and Awards

• School of Computing, Dean’s List: Fall 2021
• School of Computing, Excellent TA Award: Spring 2023 (KAIST CS420 Compilers Design), Fall 2023 (KAIST CS220 Programming Principles)